1. Field of the Invention
The present invention relates to a synchronous compensator, and more specially to a synchronous compensator for correcting the synchronization of electromagnetic waves received by a mobile telephone set such as PHS (Personal Handyphone System) terminal.
2. Description of the Background Art
The PHS system uses time slots for transmission and reception, each of which includes 240 bits. Four time slots for transmission and other four time slots for reception constitute a frame of eight time slots. When a mobile or personal station receives data transmitted from a cell station, it is required to synchronize or adjust the reception slot of the personal station to the transmission timing of the cell station. Such a timing adjustment is called a synchronous compensation.
The PHS system may utilize a method of synchronous compensation using unique words (UWs). Such a system is adapted to detect a unique word in the 240 bits of received data. Then, the detected unique word functions as a load signal. Fixed data supplied after the load signal are taken in an internal counter. The internal counter is adapted to count the 240 bits eight times to generate sync timing on the basis of a count in the counter. As the count is corrected according to the input timing of the received data, the sync timing is also corrected according to the input timing.
The conventional synchronous compensator comprises a UW detector, a bit counter, a slot counter and a sync timing generator. The received data are applied to the UW detector. The UW detector supplies the detected UW detection signal as the load timing signal to the load terminal of the modulo-240 bit counter having its full count of 240. The bit counter provides the function of indicating the bit position of received data. The bit counter has its data terminal fed with fixed data. The bit and slot counters have their clock terminal supplied with the same clock signal. The bit counter has its output terminal supplying an eight-bit [7:0] signal to one terminal of the sync timing generator. The bit counter also has its carry output terminal developing a carry output signal to the enable terminal of the slot counter. The slot counter has its full count of eight and the function of indicating the slot number. The slot counter supplies a three-bit [2:0] signal to another terminal of the sync timing generator. The sync timing generator is responsive to those signals supplied to generate several timing signals.
The above-described circuits are disclosed, for example, in U.S. Pat. Nos. 5,946,358 and 6,556,592 to Horimoto and Kasuya, respectively. The receiver of the mobile communication equipment disclosed in the Horimoto patent is adapted to generate a clock signal from a digital signal received by the demodulator and detect a UW word synchronized with the bit clock to output a UW detection signal. The comparator determines the direction of the phase shift of the detected signal with respect to the generated clock, and the counter counts the clocks for the phase shift of the bit clock with respect to the generated clock. According to direction and amount of the phase shift, the receiver varies frequency-division ratio of the programmable counter in the operational clock generator, thus establishing high-precision transmission.
In the method and circuit for correcting clock synchronization disclosed in the Kasuya patent, one signal from a frequency divider which frequency-divides a master clock by a phase difference signal for the network synchronization and another signal from another frequency divider which frequency-divides the clock on an ISDN (Integrated Service Digital Network) side by a reset release signal are supplied to a phase comparator in response to the compensation enable signal, and a phase difference signal is supplied to the other frequency divider and a third frequency divider to output an air interface clock from the latter frequency divider. Those frequency dividers are adapted for correcting clock synchronization from the state where the synchronization is established between the air interface and the ISDN network to thereby commence their frequency-dividing operation at the same timing. Thus, the PHS cell station is able to communicate with a personal station without losing the latter.
The above-described synchronous compensator circuit is adapted for correcting its synchronization whenever having detected the UW detection signal. Usually, during transmission the reception timing of data received is almost so constant that synchronization is not corrected suddenly and abruptly.
It may happen that the waves directly transmitted are intercepted by an obstacle or the like, but only the waves reflected by the obstacle are received with a time delay. In this case, what were received are waves indirectly supplied, and therefore the synchronous compensator may essentially not compensate for its erroneous synchronization. However, the waves are received without being discriminated. The conventional synchronous compensators disclosed in the above-indicated U.S. patents compensate for, whenever the compensator detects a UW word in the waves received, the erroneous synchronization even for the essentially undesired waves. If the reflected wave involves a considerably larger time delay, the compensators then correct synchronization more extensively. When this situation continues, the synchronous compensator may cause out-of-synchronism.